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 STP40N20
STB40N20 - STW40N20
N-CHANNEL 200V - 0.038 - 40A TO-220/TO-247/D2PAK LOW GATE CHARGE STripFETTM MOSFET
Table 1: General Features
TYPE STP40N20 STW40N20 STB40N20

Figure 1: Package
ID 40 A 40 A 40 A Pw 160 W 160 W 160 W
3 1 2
1 2 3
VDSS 200 V 200 V 200 V
RDS(on) < 0.045 < 0.045 < 0.045

TYPICAL RDS(on) = 0.038 GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY EXCELLENT FIGURE OF MERIT (RDS*Qg) 100% AVALANCHE TESTED
TO-220
TO-247
3
DESCRIPTION This MOSFET series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced high-efficiency isolated DC-DC converters.
1
D2PAK Figure 2: Internal Schematic Diagram
APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING UPS
Table 2: Order Codes
SALES TYPE STP40N20 STW40N20 STB40N20 MARKING P40N20 W40N20 B40N20 PACKAGE TO-220 TO-247 D2PAK PACKAGING TUBE TUBE TAPE & REEL
Rev. 3 June 2005 1/13
STB40N20 - STP40N20 - STW40N20
Table 3: Absolute Maximum ratings
Symbol VDS VDGR VGS ID ID IDM ( ) PTOT dv/dt (1) Tj Tstg Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Peak Diode Recovery voltage slope Operating Junction Temperature Storage Temperature Value 200 200 20 40 25 160 160 1.28 12 -55 to 150 Unit V V V A A A W W/C V/ns C
( ) Pulse width limited by safe operating area (1) ISD 40A, di/dt 200 A/s, VDD V(BR)DSS, T j T JMAX.
Table 4: Thermal Data
TO-220/ Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 62.5 300 0.78 50 TO-247 C/W C/W C
Table 5: Avalanche Characteristics
Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) Max Value 40 230 Unit A mJ
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ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) Table 6: On/Off
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions ID = 1mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20V VDS = VGS, ID = 250 A VGS = 10V, ID = 20 A 2 3 0.038 Min. 200 1 10 100 4 0.045 Typ. Max. Unit V A A nA V
Table 7: Dynamic
Symbol gfs (1) Ciss Coss Crss td(on) tr td(off) tr Qg Qgs Qgd Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM trr Qrr IRRM Test Conditions VDS = 15 V, ID=20 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 30 2500 510 78 20 44 74 22 75 13.2 35.5 Max. Unit S pF pF pF ns ns ns ns nC nC nC
VDD = 100 V, ID = 20 A, RG= 4.7 VGS = 10 V (Resistive Load see, Figure 17) VDD = 160V, ID = 40 A, VGS = 10V
Table 8: Source Drain Diode
Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 20 A, VGS = 0 ISD = 20 A, di/dt = 100A/s VDD = 100V, Tj = 25C (see test circuit, Figure 18) ISD = 20 A, di/dt = 100A/s VDD = 100V, Tj = 150C (see test circuit, Figure 18) 192 922 9.6 242 1440 11.9 Test Conditions Min. Typ. Max. 40 160 1.5 Unit A A V ns nC A ns nC A
(1) Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (2) Pulse width limited by safe operating area.
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STB40N20 - STP40N20 - STW40N20
Figure 3: Safe Operating Area For TO-220/ D2PAK Figure 6: Thermal Impedance For TO-220/ D2PAK
Figure 4: Safe Operating Area For TO-247
Figure 7: Thermal Impedance For TO-247
Figure 5: Output Characteristics
Figure 8: Transfer Characteristics
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STB40N20 - STP40N20 - STW40N20
Figure 9: Transconductance Figure 12: Static Drain-source On Resistance
Figure 10: Gate Charge vs Gate-source Voltage
Figure 13: Capacitance Variations
Figure 11: Normalized Gate Threshold Voltage vs Temperature
Figure 14: Normalized On Resistance vs Temperature
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STB40N20 - STP40N20 - STW40N20
Figure 15: Source-Drain Forward Characteristics
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Figure 16: Unclamped Inductive Load Test Circuit Figure 19: Unclamped Inductive Wafeform
Figure 17: Switching Times Test Circuit For Resistive Load
Figure 20: Gate Charge Test Circuit
Figure 18: Test Circuit For Inductive Load Switching and Diode Recovery Times
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STB40N20 - STP40N20 - STW40N20
TO-220 MECHANICAL DATA
DIM. A b b1 c D E e e1 F H1 J1 L L1 L20 L30 mm. MIN. 4.40 0.61 1.15 0.49 15.25 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 TYP MAX. 4.60 0.88 1.70 0.70 15.75 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 MIN. 0.173 0.024 0.045 0.019 0.60 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 0.645 1.137 0.151 0.116 inch TYP. MAX. 0.181 0.034 0.066 0.027 0.620 0.409 0.106 0.202 0.052 0.256 0.107 0.551 0.154
oP
Q
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STB40N20 - STP40N20 - STW40N20
TO-247 MECHANICAL DATA
mm. MIN. 4.85 2.20 1.0 2.0 3.0 0.40 19.85 15.45 5.45 14.20 3.70 18.50 3.55 4.50 5.50 3.65 5.50 0.140 0.177 0.216 14.80 4.30 0.560 0.14 0.728 0.143 0.216 TYP MAX. 5.15 2.60 1.40 2.40 3.40 0.80 20.15 15.75 MIN. 0.19 0.086 0.039 0.079 0.118 0.015 0.781 0.608 0.214 0.582 0.17 inch TYP. MAX. 0.20 0.102 0.055 0.094 0.134 0.03 0.793 0.620
DIM. A A1 b b1 b2 c D E e L L1 L2 oP oR S
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STB40N20 - STP40N20 - STW40N20
D2PAK MECHANICAL DATA TO-247 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 B B2 C C2 D D1 E E1 G L L2 L3 M R V2 0 4.88 15 1.27 1.4 2.4 0.4 4 10 8.5 5.28 15.85 1.4 1.75 3.2 0.192 0.590 0.050 0.055 0.094 0.015 4.4 2.49 0.03 0.7 1.14 0.45 1.23 8.95 8 10.4 0.393 0.334 0.208 0.625 0.055 0.068 0.126 TYP MAX. 4.6 2.69 0.23 0.93 1.7 0.6 1.36 9.35 MIN. 0.173 0.098 0.001 0.027 0.044 0.017 0.048 0.352 0.315 TYP. MAX. 0.181 0.106 0.009 0.036 0.067 0.023 0.053 0.368 inch
3
1
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STB40N20 - STP40N20 - STW40N20
D2PAK FOOTPRINT
TAPE AND REEL SHIPMENT
REEL MECHANICAL DATA
DIM. A B C D G N T 1.5 12.8 20.2 24.4 100 30.4 26.4 13.2 mm MIN. MAX. 330 0.059 0.504 0.520 0795 0.960 1.039 3.937 1.197 BULK QTY 1000 inch MIN. MAX. 12.992
TAPE MECHANICAL DATA
DIM. A0 B0 D D1 E F K0 P0 P1 P2 R T W mm MIN. 10.5 15.7 1.5 1.59 1.65 11.4 4.8 3.9 11.9 1.9 50 0.25 23.7 24.3 MAX. 10.7 15.9 1.6 1.61 1.85 11.6 5.0 4.1 12.1 2.1 inch MIN. MAX. 0.413 0.421 0.618 0.626 0.059 0.063 0.062 0.063 0.065 0.073 0.449 0.456 0.189 0.197 0.153 0.161 0.468 0.476 0.075 0.082 1.574 0.35 0.0098 0.0137 0.933 0.956
BASE QTY 1000
* on sales type
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STB40N20 - STP40N20 - STW40N20
Table 9: Revision History
Date 27-Sep-2004 03-Feb-2005 03-Jun-2005 Revision 1 2 3 First Release. Complete Version Update with D2PAK Description of Changes
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STB40N20 - STP40N20 - STW40N20
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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